Dynamically determining memory access burst length

ABSTRACT

Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory read requests have been sent to a memory device in a read mode of a data bus, the memory controller determines a threshold number of memory write requests to send to the memory device in an upcoming write mode is a number of outstanding memory write requests. Alternatively, the memory controller determines the threshold number of memory write requests to send to the memory device in an upcoming write mode is a maximum value of the number of outstanding memory write requests and a programmable value of the write burst length stored in a control register. Therefore, the write burst length is determined dynamically. Similarly, the read burst length is determined dynamically when the write mode ends.

BACKGROUND Description of the Related Art

Computing systems are typically designed with one or more processorsconfigured to process program instructions and use a memory device forstorage of data. Typically, the processors are coupled to the memorydevice via a memory controller. When a processor generates a memory readrequest or memory write request, the request is conveyed from theprocessor to the memory controller where they are stored in one or morequeues while they await further processing. The memory controller thenschedules the received requests for processing by generating read andwrite transactions to the memory device(s).

In many systems, a data bus connecting the memory controller to thememory device is configured to communicate data in only one direction ata time. For example, when the memory controller sends data to be storedin the memory device, the data bus operates to communicate data from thememory controller to the memory device. Conversely, when the memorycontroller is receiving data from the memory device, the data busoperates to communicate data from the memory device to the memorycontroller. When a change is made between operating the bus in onedirection to operating the bus in the other direction, the change indirection is generally referred to as a “bus turnaround.” While this busturnaround occurs, no data can be transmitted in either direction.Consequently, the effective bandwidth of the bus during the busturnaround period is zero. As such, these bus turnaround periods reducethe overall bandwidth of the bus, with more bus turnarounds resulting ina lower overall bandwidth for the bus. Because the memory controllerschedules processing of the read and write requests, how the requestsare scheduled has a direct impact on the overall effective bandwidth ofthe data bus.

In view of the above, efficient methods and systems for performingefficient memory accesses for a computing system are desired.

BRIEF DESCRIPTION OF THE DRAWINGS

The advantages of the methods and mechanisms described herein may bebetter understood by referring to the following description inconjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of one embodiment of a computing system.

FIG. 2 is a block diagram of one embodiment of a memory controller.

FIG. 3 is a flow diagram of one embodiment of a method for performingefficient memory accesses for a computing system.

FIG. 4 is a flow diagram of another embodiment of a method forperforming efficient memory accesses for a computing system.

While the invention is susceptible to various modifications andalternative forms, specific embodiments are shown by way of example inthe drawings and are herein described in detail. It should beunderstood, however, that drawings and detailed description thereto arenot intended to limit the invention to the particular form disclosed,but on the contrary, the invention is to cover all modifications,equivalents and alternatives falling within the scope of the presentinvention as defined by the appended claims.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following description, numerous specific details are set forth toprovide a thorough understanding of the methods and mechanisms presentedherein. However, one having ordinary skill in the art should recognizethat the various embodiments may be practiced without these specificdetails. In some instances, well-known structures, components, signals,computer program instructions, and techniques have not been shown indetail to avoid obscuring the approaches described herein. It will beappreciated that for simplicity and clarity of illustration, elementsshown in the figures have not necessarily been drawn to scale. Forexample, the dimensions of some of the elements may be exaggeratedrelative to other elements.

Various systems, apparatuses, methods, and computer-readable mediums forperforming efficient memory accesses for a computing system aredisclosed. In one embodiment, a computing system includes one or morecomputing resources and external system memory, such as one of a varietyof types of random access memory (e.g., DRAM or otherwise). Examples ofthe computing resources include a general-purpose central processingunit (CPU), a graphics processing unit (GPU), an accelerated processingunit (APU), and so forth. The computing resources generate memoryrequests. In various embodiments, a given computing resource includes acache memory sub system.

When a computing resource generates a memory access request (generallyreferred to herein as a “memory request”), the memory request isconveyed to a memory device via a memory controller. The memorycontroller is coupled to the memory device via a data bus (or “memory”bus). In various embodiments the memory device is off-chip (i.e., is adistinct component from the processors and/or memory controller). Inother embodiments, the memory is on-chip. If the computing systemincludes multiple memory devices, then the address spaces aredistributed among the multiple memory devices by the operating system.The memory controller supports mapping between the request addresses ofthe computing resources and addresses pointing to storage locations inthe memory device(s). In some embodiments, a memory controller isconnected to a single memory device. In other embodiments, a memorycontroller is connected to multiple memory devices. In variousembodiments, the memory controller includes one or more queues forstoring memory requests. In an embodiment, the memory controllerincludes a read queue for storing memory read requests and a separatewrite queue for storing memory write requests. In other embodiments, thememory controller includes a unified queue for storing both memory readrequests and memory write requests. In yet other embodiments, the memorycontroller includes one or more queues for storing received memoryrequests and a separate queue for storing scheduled memory requestsselected from the one or more queues. Further, in various embodiments,the memory controller supports out-of-order issue of the memory requeststo the memory device based on priorities, target addresses, or otherconsiderations.

In various embodiments, the memory controller includes control andstatus registers and a control unit with control logic for storingthresholds and other data used for control decisions. The control logicin the memory controller determines which one of a read mode and a writemode is a current mode for the data bus and the memory device. In anembodiment, a threshold may be established (e.g., via a programmableregister or otherwise) that indicates a number of memory requests tosend from the memory controller to the memory device prior to a data busturnaround. This threshold number of memory requests to send is referredto as the “burst length”. As noted above, in various embodiments thedata bus can only communicate data in one direction at a time. In orderto change from one direction to the other, a data bus turnaround must beperformed during which no data can be transferred via the bus. Invarious embodiments, the data bus utilizes a bidirectional shared-busstructure. When a bus driver stops driving information in a givendirection on the data bus, a delay occurs before another bus driver isable to drive information in the opposite direction.

In some embodiments, a count of remaining read requests to send isupdated when memory read requests are sent from the memory controller tothe memory device. The count is incremented or decremented depending onthe initial value of the count, which may increment from zero to thethreshold number of memory read requests, or read burst length, oralternatively decrement from the read burst length to zero. In variousembodiments, a write count is updated in a similar manner based on theinitial value of count when memory write requests are sent from thememory controller to the memory device. For sending write requests tothe memory device, a write burst length is used.

As used herein, “memory read requests” are memory requests configured toread data from the memory device and may also be referred to as readrequests. Similarly, “memory write requests” are memory requestsconfigured to write data to the memory device and may also be referredto as write requests. For read requests, a read response sent from thememory device to the memory controller includes the data that wasrequested in the read request. Similarly, the read response sent fromthe memory controller to the computing resource which generated the readrequest includes the data requested in the read request. For writerequests, the write response sent from the memory controller to thecomputing resource which generated the write request includes anacknowledgment that the write operation completed. In variousembodiments, no acknowledgment is sent from the memory device to thememory controller. Therefore, in an embodiment, the write request isconsidered completed when the write data following the write request issent from the memory controller to the memory device.

When the control logic determines that a threshold number of memoryrequests (the burst length) has been sent from the memory controller tothe memory device during a current mode, the control logic indicates itis time for a data bus turnaround and changes the current mode toanother mode of the read mode and the write mode. For example, when thecurrent mode is a read mode and the control logic determines thethreshold number of memory read requests (the read burst length) havebeen sent from the memory controller to the memory device, the controllogic indicates it is time for a data bus turnaround and changes thecurrent mode of the memory controller from the read mode to the writemode. While this data bus turnaround occurs, no data can be transferredvia the data bus.

In various embodiments, one or more of the read burst length and thewrite burst length are dynamically determined rather than staticallydetermined. In one embodiment, when the control logic in the memorycontroller determines it is time to switch from a read mode to a writemode, the control logic determines a threshold number of memory writerequests to send to the memory device in an upcoming write mode is equalto a number of outstanding memory write requests (e.g., the number ofreceived write requests in a pending queue). Therefore, as the number ofpending write requests may vary during processing, the write burstlength may likewise vary during processing and is determined dynamicallyduring each mode switch of the data bus and memory device from a readmode to a write mode.

In another embodiment, when the control logic in the memory controllerdetermines it is time to switch from a read mode to a write mode, thecontrol logic determines and sets the number of memory write requests tosend to the memory device in an upcoming write mode equal to the greaterof the number of outstanding memory write requests and a threshold valueof the write burst length (e.g., a programmable or predetermined value).Therefore, again, the write burst length is determined dynamicallyduring a mode switch of the data bus and memory device from a read modeto a write mode.

In yet other embodiments, when the control logic in the memorycontroller determines it is time for any switch of the current mode(e.g., read-to-write, write-to-read), the control logic determines athreshold number of memory requests to send to the memory device in anupcoming write mode or read mode is the greater of the number ofoutstanding memory requests of a type associated with the upcoming modeand a programmable value of the burst length stored in a controlregister associated with the upcoming mode. Therefore, each of the readburst length and the write burst length is determined dynamically duringeach corresponding mode switch of the data bus and memory device.

Referring to FIG. 1, a generalized block diagram of one embodiment of acomputing system 100 is shown. As shown, computing system 100 includescommunication fabric 120 between each of memory controller 130 andcomputing resources 110. In the illustrated embodiment, the computingresources include central processing unit (CPU) 112, graphics processingunit (GPU) 114 and Hub 116. Hub 116 is used for communicating withMultimedia Engine 118. Although a single memory controller 130 is shown,in other embodiments, another number of memory controllers are used incomputing system 100. Memory controller 130 receives memory requestsfrom computing resources 110 via the communication fabric 120 and sendsthe memory requests to one or more of disk memory 162 and system memory,which is implemented a random access memory (RAM) 170. Memory controller130 also receives responses from RAM 170 and disk memory 162 and sendsthe responses to a corresponding source of the request in computingresources 110.

In some embodiments, the components of computing system 100 areindividual dies on an integrated circuit (IC), such as asystem-on-a-chip (SOC). In other embodiments, the components areindividual dies in a system-in-package (SiP) or a multi-chip module(MCM). In one embodiment, computing system 100 is a stand-alone systemwithin a mobile computer, a smart phone, a smartwatch, or a tablet; adesktop; a server; or other. The CPU 112, GPU 114 and Multimedia Engine118 are examples of computing resources capable of generating memoryrequests. Although not shown, in other embodiments, other types ofcomputing resources are included in computing resources 110.

Each of the one or more processor cores in CPU 112 includes circuitryfor executing instructions according to a given selected instruction setarchitecture (ISA). In various embodiments, each of the processor coresin CPU 112 includes a superscalar, multi-threaded microarchitecture usedfor processing instructions of the given ISA. In an embodiment, GPU 114includes a high parallel data microarchitecture with a significantnumber of parallel execution lanes. In one embodiment, themicroarchitecture uses single-instruction-multiple-data (SIMD) pipelinefor the parallel execution lanes. Multimedia Engine 118 includesprocessors for processing audio data and visual data for multimediaapplications.

In one example, an accelerated processing unit (APU), a displaycontroller, an audio processor, and so forth, are additional candidatesto be included in processing units 110. An example of an APU is a CPUintegrated on a same die with a GPU, a FPGA, or other processing unit,thus improving data transfer rates between these units while reducingpower consumption. In other embodiments, the APU includes videoprocessing and other application-specific accelerators.

In various embodiments, communication fabric 120 transfers traffic backand forth between processing units 110 and memory controller 130 andincludes interfaces for supporting respective communication protocols.In some embodiments, communication fabric 120 includes at least queuesfor storing requests and responses, selection logic for arbitratingbetween received requests before sending requests across an internalnetwork, logic for building and decoding packets, and logic forselecting routes for the packets.

In some embodiments, the address space of the computing system 100 isdivided among at least CPU 112, GPU 114 and Hub 116 and one or moreother components such as input/output peripheral devices (not shown) andother types of computing resources. Memory maps are maintained fordetermining which addresses are mapped to which component, and hence towhich one of CPU 112, GPU 114 and Hub 116 a memory request for aparticular address should be routed.

As software applications access more and more data, the memory subsystemis utilized more heavily. One or more of the computing resources withinprocessing units 110 include cache memory subsystems to reduce memorylatencies for a respective processor core. As used herein, the term“access” refers to performing a memory read request or a memory writerequest operation that results in a cache hit if the requested data of acorresponding request address resides in the cache. Alternatively, thememory request results in a cache miss if the requested data does notreside in the cache. If a cache miss occurs, then a memory request isgenerated and transmitted to the memory controller 130. The memorycontroller 130 translates an address corresponding to the requestedblock and sends the memory request to RAM 170 through the memory bus150.

In an embodiment, RAM 170 includes a multi-channel memory architecture.This type of architecture increases the transfer speed of data to thememory controller 130 by adding more channels of communication betweenthem. In an embodiment, the multi-channel architecture utilizes multiplememory modules and a motherboard and/or a card capable of supportingmultiple channels. In some embodiments, RAM 170 is a type of dynamicrandom-access memory that stores each bit of data in a separatecapacitor within an integrated circuit. In another embodiment, RAM 170utilizes three-dimensional integrated circuits (3D ICs) to providesystem memory.

As shown, RAM 170 includes multiple memory array banks 174A-174B. Eachone of the banks 174A-174B include a respective one of the row buffers172A-172B. Each one of the row buffers 172A-172B stores data in anaccessed row of the multiple rows within the memory array banks174A-174B. The accessed row is identified by a DRAM address in thereceived memory request. Control logic within RAM 170 performs complextransactions such as activation and precharge of data and control lineswithin RAM 170 once to access an identified row and once to put back themodified contents stored in the row buffer to the identified row. In anembodiment, the complex transactions are performed based on commandssent from the memory controller 130. In various embodiments, RAM 170includes one or more memory channels, one or more memory modules ordevices per channel, one or more ranks per memory module, one or morebanks per rank, and one or more rows per bank. Typically, each rowstores a page of data. The size of the page is chosen based on designconsiderations. The page can be one kilobyte (1 KB), four kilobytes (4KB), or any size based on design choices.

Accesses of RAM 170 generally include an activation stage, prechargestage, switches to different banks between adjacent accesses, switchesto different ranks between adjacent accesses, and so forth. In addition,as already noted, no data can be transmitted via the data bus during adata bus turnaround. For example, when write requests corresponding to awrite mode have been serviced and the end of the write mode is reachedthe read mode begins after the data bus turnaround completes. Similarly,when read requests corresponding to the read mode have been serviced andthe end of the read mode is reached, another write mode begins after thedata bus turnaround completes.

As shown, memory controller 130 includes request queues 132 for queuingmemory requests received from processing units 110 via communicationfabric 120. Memory controller 130 also has a response queue(s) 134 forstoring responses received from RAM 170. In an embodiment, requestqueues 132 include one or more queues for storing memory requests. Inanother embodiment, request queues 132 include a read queue for storingmemory read requests and a separate write queue for storing memory writerequests. In other embodiments, request queues 132 include a unifiedqueue for storing both memory read requests and memory write requests.Still further, request queues 132 include one or more queues for storingreceived memory requests and a separate queue for storing scheduledmemory requests selected from the one or more queues.

Schedulers 136 include logic (e.g., circuitry) for selecting memoryrequests stored in request queues 132 for issue to RAM 170. In variousembodiments, schedulers 136 in memory controller 130 schedule the issueof the stored memory requests based on a quality-of-service (QoS) orother priority information, age, a process or thread identifier (ID),and a relationship with other stored requests such as targeting a samememory channel, targeting a same rank, targeting a same bank and/ortargeting a same page. In various embodiments, schedulers 136 scheduleoutstanding memory requests based at least upon reducing a number ofpage conflicts and a number of page misses.

In various embodiments, memory bus 150 supports sending data traffic ona data bus in a single direction while in one mode of a read mode and awrite mode, and then sends data traffic in the opposite direction whilein the other mode. In an embodiment, memory bus 150 utilizes at least acommand bus and a data bus, and memory bus 150 supports a read mode forsending data traffic on the data bus from RAM 170 to memory controller130. Additionally, memory bus 150 supports a write mode for sending datatraffic on the data bus from memory controller 130 to RAM 170.

Control logic in memory controller 130 determines which one of a readmode and a write mode is a current mode for the data bus in memory bus150. Each mode has a threshold number of memory requests to send fromthe memory controller to the memory device prior to a data busturnaround. This threshold number of memory requests to send is theburst length. When the control logic determines the threshold number ofmemory requests have been sent in the current mode, the control logicindicates it is time for a data bus turnaround and changes the currentmode to another mode of the read mode and the write mode.

In one embodiment, when control logic in memory controller 130determines it is time to switch from a read mode to a write mode, burstlength logic 138 dynamically determines a threshold number of memorywrite requests to send to RAM 170 in an upcoming write mode. In variousembodiments, this dynamically determined number is set equal to a numberof outstanding memory write requests stored in request queues 132.Therefore, the write burst length is determined dynamically by burstlength logic 138 during each mode switch of the data bus and memorydevice from a read mode to a write mode. In various embodiments, whencontrol logic in memory controller 130 determines it is time to switchfrom a read mode to a write mode, burst length logic 138 dynamicallydetermines a threshold number of memory write requests to send to RAM170 is equal to the greater of a number of memory write requests thatare outstanding (e.g., are currently stored and awaiting servicing inthe memory controller) and a programmable (or predetermined) value for awrite burst length stored in a control register.

In yet other embodiments, when control logic in memory controller 130determines it is time for any switch of the current mode (e.g.,read-to-write, write-to-read), burst length logic 138 determines athreshold number of memory requests to send to RAM 170 in an upcomingwrite mode or read mode is the greater of a number of outstanding memoryrequests of a type associated with the upcoming mode and a programmable(or predetermined) value of the burst length stored in a controlregister associated with the upcoming mode.

Referring to FIG. 2, a generalized block diagram of one embodiment of amemory controller 200 is shown. In the illustrated embodiment, memorycontroller 200 includes an interface 210 to computing resources via acommunication fabric, queues 220 for storing received memory requestsand received responses, control unit 250 and an interface 280 to amemory device via at least a data bus of a memory bus. Each ofinterfaces 210 and 280 supports respective communication protocols.

In an embodiment, queues 220 includes a read queue 232 for storingreceived read requests and a separate write queue 234 for storingreceived write requests. In other embodiments, queues 220 includes aunified queue for storing both memory read requests and memory writerequests. In one embodiment, queues 220 includes queue 236 for storingscheduled memory requests selected from read queue 232, write queue 234or a unified queue if one is used.

In some embodiments, read scheduler 252 includes arbitration logic forselecting read requests from the read queue 220 out-of-order. Readscheduler 252 schedules the issue of the stored requests within the readqueue 220 to the memory device based on any of a variety of conditions,such as a quality-of-service (QoS) or other priority information, age, aprocess or thread identifier (ID), and a relationship with other storedrequests such as targeting a same memory channel, targeting a same rank,targeting a same bank and/or targeting a same page. Write scheduler 254includes similar selection logic for the write queue 234. In anembodiment, response scheduler 256 includes similar logic for issuing,based on priorities, responses to the computing resources, which werereceived from the memory device.

In some embodiments, control registers 270 store an indication of acurrent mode for a data bus coupled to a memory device (not shown). Forexample, in various embodiments, the memory data bus and memory deviceare configured to support a read mode and a write mode. As discussedabove, data transfers via the data bus can only move in a singledirection at any given time. When switching from one mode to the other,no data can be transferred via the data bus. In various embodiments,control registers 270 store a number of read requests (read burstlength) to send during the read mode. In some embodiments, the controlregisters 270 also store a write bust length. In some embodiments, theburst length is the same for each of the read mode and the write mode.In other embodiments, two different burst lengths are used for the readmode and the write mode.

In one embodiment, when control logic in control unit 250 determines itis time to switch from a read mode to a write mode, write burst lengthlogic 262 determines the number of memory write requests to send to thememory device in an upcoming write mode is equal to a number ofoutstanding memory write requests stored in queues 220. Therefore, thewrite burst length is determined dynamically during each mode switch ofthe data bus and memory device from a read mode to a write mode. Inanother embodiment, when the control logic in the memory controllerdetermines it is time to switch from a read mode to a write mode, writeburst length logic 262 determines the threshold number of memory writerequests to send to the memory device in an upcoming write mode is equalto the greater of a number of outstanding memory write requests and aprogrammable (or predetermined) value of the write burst length.

In yet other embodiments, when the control logic in the memorycontroller determines it is time for any switch from the current mode(e.g., read-to-write, write-to-read), one of read burst length logic 260and write burst length logic 262 determines a threshold number of memoryrequests to send to the memory device in an upcoming read mode or writemode is the greater of a number of outstanding memory requests of a typeassociated with the upcoming mode and a programmable (or predetermined)value of the burst length. In various embodiments, the above describedprogrammable or predetermined values may be stored in control registers270. In this manner, each of the read burst length and the write burstlength is determined dynamically during system operation.

Referring now to FIG. 3, one embodiment of a method 300 for performingefficient memory accesses for a computing system is shown. For purposesof discussion, the steps in this embodiment (as well as in FIG. 4) areshown in sequential order. However, it is noted that in variousembodiments of the described methods, one or more of the elementsdescribed are performed concurrently, in a different order than shown,or are omitted entirely. Other additional elements are also performed asdesired. Any of the various systems or apparatuses described herein areconfigured to implement method 300.

One or more computing resources execute computer programs, or softwareapplications. Examples of a computing resource are given earlier. Thecomputing resource determines a given memory request misses within acache memory subsystem within the computing resource. The computingresource sends the memory request to system memory such as DRAM via amemory controller. The memory controller stores memory requests in oneor more queues (block 302).

The memory requests are scheduled based on at least priorities andtargets of the memory requests (block 304). As described earlier, invarious embodiments, memory requests are scheduled for issue based onone or more of a quality-of-service (QoS) or other priority information,age, a process or thread identifier (ID), and a relationship with otherstored requests such as targeting a same memory channel, targeting asame rank, targeting a same bank and/or targeting a same page, orotherwise. If a burst length of the current mode has not been reached(“no” branch of the conditional block 306), then additional memoryrequests according to the current mode are sent to the system memory(block 308). However, if the burst length of the current mode has beenreached (“yes” branch of the conditional block 306), then the currentmode is terminated and which one of a read mode and a write mode is thenext mode for the system memory is determined (block 310).

If the next mode is a read mode (“read” branch of the conditional block312), then the read burst length is set to a given value (block 314), adata bus turnaround (block 316) is performed, and the read requests areserviced. In various embodiments, the given value is a predeterminedvalue. In one embodiment, a programmable control register is read todetermine the read burst length. Therefore, in some embodiments, theread burst length is determined statically in contrast to the writeburst length being determined dynamically. However, in otherembodiments, each of the read burst length and the write burst length isdetermined dynamically as described above and in FIG. 4. If the nextmode is a write mode (“write” branch of the conditional block 312), thena number of write requests to be serviced is determined (block 318). Inone embodiment, a “snapshot” of the current number of write requests ina queue (or other storage device) that have been received and arepending is taken. At any given time, this number will vary duringoperation of the system. The determined number of pending writes is thenused to set a burst length for a write burst (block 320) and after thebus turnaround is completed (block 316), the write burst is performed(block 308). In various embodiments, the burst length is fixed at thenumber determined by the above mentioned snapshot—even if other writetransactions are received before the write burst is completed. In otherembodiments, one or more additional write transactions may be added tothe write burst if such additional writes are received before completionof the write burst.

Referring to FIG. 4, another embodiment of a method 400 for performingefficient memory accesses for a computing system is shown. As shown inblock 402, a burst length for the current mode is reached. Which one ofa read mode and a write mode is the next mode for the system memory isdetermined (block 404). In some embodiments, the next mode is implicitlydetermined to be the opposite of the current mode. In an embodiment, afirst number is set to a given burst length of an access type of thenext mode (block 406). In various embodiments, the given value is apredetermined value. In one embodiment, a programmable registerassociated with the next mode is read to determine the first number(block 406). In addition, a second number of scheduled outstandingrequests of an access type of the next mode is also determined (block408). In one embodiment, a “snapshot” of the current number of pendingwrite transactions in a queue is taken. At any given time, this numberwill vary during operation of the system. In this manner, the secondnumber is determined dynamically. In some embodiments, a weight isassociated with each write transaction stored in the queue. In anembodiment, the weight is set based on one or more of aquality-of-service (QoS) or other priority information, age, a processor thread identifier (ID), a determination of whether the writetransaction can be grouped with other write transactions to reduce pageconflicts and page misses, and so forth. Therefore, the second number isa weighted sum of the current number of write transactions that havebeen received and are pending. In an embodiment, the first number isadjusted based on the weights. For example, the programmable valuestored in the configuration register associated with the next mode isselected based on knowledge of the ranges of the weights. Accordingly,the first number suggesting a given burst length of an access type ofthe next mode accounts for the use of the weights similar to the secondnumber. In various embodiments, the burst length for the next mode isset to the greater of the first number and the second number (block410). After the data bus turnaround is complete (block 412), thescheduled memory requests of the access type of the next mode are thensent until the burst length is reached (block 414).

In various embodiments, program instructions of a software applicationare used to implement the methods and/or mechanisms previouslydescribed. The program instructions describe the behavior of hardware ina high-level programming language, such as C. Alternatively, a hardwaredesign language (HDL) is used, such as Verilog. The program instructionsare stored on a non-transitory computer readable storage medium.Numerous types of storage media are available. The storage medium isaccessible by a computing system during use to provide the programinstructions and accompanying data to the computing system for programexecution. The computing system includes at least one or more memoriesand one or more processors configured to execute program instructions.

It should be emphasized that the above-described embodiments are onlynon-limiting examples of implementations. Numerous variations andmodifications will become apparent to those skilled in the art once theabove disclosure is fully appreciated. It is intended that the followingclaims be interpreted to embrace all such variations and modifications.

What is claimed is:
 1. A memory controller comprising: a first interfacefor receiving memory access requests; a second interface for sendingmemory access requests to a memory device; one or more queues configuredto store memory access requests; and control logic; wherein in responseto determining an end of a read mode during which read requests are sentvia the second interface, the control logic is configured to: terminatethe read mode and begin a write mode during which write requests aresent via the second interface; dynamically determine a number of writerequests to send as part of a write burst, wherein dynamicallydetermining said number comprises determining how many write requestsare currently pending; send said number of write requests via the secondinterface; and terminate the write mode and begin the read mode, inresponse to determining said number of write requests have been sent. 2.The memory controller as recited in claim 1, wherein dynamicallydetermining the number of write requests comprises setting the number ofwrite requests to send as part of the write burst equal to a greater ofthe number of write requests currently pending and a threshold number.3. The memory controller as recited in claim 2, wherein the controllogic is configured to send one or more write transactions as part ofthe write burst that arrived after the number of write requests to sendwas determined.
 4. The memory controller as recited in claim 1, whereinto determine how many write requests are currently pending, the controllogic is configured to determine how many write requests are currentlystored in a queue of the one or more queues.
 5. The memory controller asrecited in claim 1, wherein the threshold number is a programmable valuestored in a register.
 6. The memory controller as recited in claim 1,wherein the control logic is further configured to schedule outstandingmemory access requests based on at least one of reducing a number ofpage conflicts and reducing a number of page misses in memory accessrequests sent to the memory device.
 7. The memory controller as recitedin claim 1, wherein the second interface is connected to a plurality ofmemory devices, and wherein the control logic is further configured toschedule outstanding memory access requests based at least in part onreducing a number of switches between ranks of the plurality of memorydevices.
 8. A method, comprising: receiving from one or more computingresources, memory access requests for data stored in a memory device;storing, by a memory controller, the memory access requests in one ormore queues; in response to determining an end of a read mode duringwhich read requests are sent to the memory device: terminating, by thememory controller, the read mode and beginning a write mode during whichwrite requests are sent to the memory device; dynamically determining,by the memory controller, a number of write requests to send as part ofa write burst, wherein dynamically determining said number comprisesdetermining how many write requests are currently pending; sending, bythe memory controller, said number of write requests to the memorydevice; and terminating, by the memory controller, the write mode andbegin the read mode, in response to determining said number of writerequests have been sent.
 9. The method as recited in claim 8, whereindynamically determining the number of write requests comprises settingthe number of write requests to send as part of the write burst equal toa greater of the number of write requests currently pending and athreshold number.
 10. The method as recited in claim 9, furthercomprising sending one or more write transactions as part of the writeburst that arrived after the number of write requests to send wasdetermined.
 11. The method as recited in claim 8, wherein determininghow many write requests are currently pending comprises determining howmany write requests are currently stored in a queue of the one or morequeues.
 12. The method as recited in claim 8, wherein the thresholdnumber is a programmable value stored in a register.
 13. The method asrecited in claim 8, wherein the method further comprises schedulingoutstanding memory access requests based on at least one of reducing anumber of page conflicts and a number of page misses in memory accessrequests sent to the memory device.
 14. The method as recited in claim8, further comprising: sending memory access requests to a plurality ofmemory devices; and scheduling outstanding memory access requests basedat least in part on reducing a number of switches between ranks of theplurality of memory devices.
 15. A computing system comprising: a memorydevice configured to store data; one or more computing resources, eachconfigured to generate memory access requests for the data; and a memorycontroller coupled to the memory device, wherein the memory controlleris configured to: store the memory access requests in one or morequeues; in response to determining an end of a read mode during whichread requests are sent to the memory device, the memory controller isconfigured to: terminate the read mode and begin a write mode duringwhich write requests are sent via the second interface; dynamicallydetermine a number of write requests to send as part of a write burst,wherein dynamically determining said number comprises determining howmany write requests are currently pending; send said number of writerequests to the memory device; and terminate the write mode and beginthe read mode, in response to determining said number of write requestshave been sent.
 16. The computing system as recited in claim 15, whereindynamically determining the number of write requests comprises settingthe number of write requests to send as part of the write burst equal toa greater of the number of write requests currently pending and athreshold number.
 17. The computing system as recited in claim 16,wherein the memory controller is configured to send one or more writetransactions as part of the write burst that arrived after the number ofwrite requests to send was determined.
 18. The computing system asrecited in claim 15, wherein to determine how many write requests arecurrently pending, the memory controller is configured to determine howmany write requests are currently stored in a queue of the one or morequeues.
 19. The computing system as recited in claim 15, wherein thethreshold number is a programmable value stored in a register.
 20. Thecomputing system as recited in claim 15, wherein the memory controlleris further configured to schedule outstanding memory access requestsbased on at least one of reducing a number of page conflicts andreducing a number of page misses in memory access requests sent to thememory device.